A power supply unit that uses batteries as a power source is usually provided with a protection IC (integrated circuit), called a power source monitoring IC, to stabilize the operation of the unit. The protection achieved by this IC includes protection against overdischarge and overcurrent, and such protection requires the use of delay circuits to eliminate external noises.
A block diagram of the principal portions of a conventional power supply unit that uses batteries (such a power supply unit is also referred to as a "battery pack") is shown in FIG. 7. In FIG. 7, numeral 1 represents a power source consisting of one or more batteries (lithium-ion cells), numeral 2 represents a discharge control FET (field-effect transistor), numeral 3 represents an FET control circuit, numeral 5 represents a first delay circuit, numeral 7 represents a second delay circuit, numeral 8 represents an OR circuit, numeral 9 represents a positive output terminal, numeral 10 represents a negative output terminal, and numeral 11 represents an external load connected to the terminals 9 and 10.
Numeral 4 represents a power source monitoring circuit, realized with a comparator, for detecting overdischarge. This circuit 4 monitors the voltage of the power source 1, and, when that voltage drops below a predetermined voltage V.sub.ref1, it outputs a high level. This output is fed through the first delay circuit 5, that is, with a delay of a predetermined length of time T1, to the OR circuit 8. In response, the OR circuit 8 outputs an OFF signal to the FET control circuit 3 (i.e. the OR circuit outputs a high level). On receiving the OFF signal, the FET control circuit 3 turns off the discharge control FET 2. In this way, the power source 1 is protected against overdischarge.
Numeral 6 represents a power source monitoring circuit for detecting overcurrent. This circuit 6 monitors the current flowing out of the power source 1 by monitoring the voltage appearing across the ON resistance of the discharge control FET 2, and, when that voltage exceeds a predetermined voltage V.sub.ref2, it outputs a high level. This output is fed through the second delay circuit 7, that is, with a delay of a predetermined length of time T2, to the OR circuit 8. In response, the OR circuit 8 outputs an OFF signal to the FET control circuit 3 (i.e. the OR circuit outputs a high level). On receiving the OFF signal, the FET control circuit 3 turns off the discharge control FET 2. In this way, the power source 1 is protected against overcurrent discharge.
In case of overcurrent, however, the internal impedance of the power source 1 varies in such a way that the voltage of the power source 1 lowers, with the result that the power source 1 is erroneously judged to be in the state of overdischarge. To prevent this, the delay time T1 in the first delay circuit 5 needs to be set longer than the delay time T2 in the second delay circuit 7.
As described above, according to the prior art, the delay time for overdischarge detection and the delay time for overcurrent detection need to be set differently, and therefore it is necessary to provide two separate delay circuits for overdischarge detection and for overcurrent detection with extra cost. Moreover, since delay circuits include capacitors as their circuit elements, the prior art, which requires the use of two delay circuits, inevitably requires larger areas for the IC chip and for the circuit board on which to mount the IC chip. This leads to limitations on the size of batteries that can be used, and thus to the reduction of the capacity of the power source.
In addition, variations of the constants of capacitors or other components from unit to unit result in variations of the delay times, and therefore, in the worst case, the relationship between the delay times of the two delay circuits may even be reversed. In such a case, it is impossible to detect overdischarge and overcurrent correctly.